-- EASE/HDL begin --------------------------------------------------------------
-- 
-- Architecture 'rtl' of entity 'reg_dcf_data'.
-- 
--------------------------------------------------------------------------------
-- 
-- Copy of the interface declaration:
-- 
--   port(
--     clk          : in     std_logic;
--     data_ebl     : in     std_logic;
--     dcf_data     : in     std_logic_vector(58 downto 0);
--     dcf_data_reg : out    std_logic_vector(58 downto 0);
--     reset_n      : in     std_logic);
-- 
-- EASE/HDL end ----------------------------------------------------------------

architecture rtl of reg_dcf_data is

SIGNAL loc_reg : std_logic_vector(58 DOWNTO 0);  
begin
p1:PROCESS(clk,reset_n) 
BEGIN          
	IF reset_n = '0' THEN 
        loc_reg <= (OTHERS => '0');    
    ELSIF (clk'EVENT AND clk = '1') THEN 
		IF data_ebl='1' THEN
	   	loc_reg <=  dcf_data;  
		END IF;
	END IF;

END PROCESS;
dcf_data_reg <= loc_reg;
end architecture rtl ; -- of reg_dcf_data

